Generally field effect transistors (FET), specifically MOS transistors are semiconductor devices that comprise a source terminal and a drain terminal and an intermediate channel region, in which a conductive channel forms upon applying an appropriate control voltage to a gate electrode structure. The gate electrode structure in turn includes a gate electrode and a gate dielectric layer that separates the gate electrode from the channel region. By applying a voltage across the gate electrode and the semiconductor body that is connected to the channel region, exceeding the threshold voltage of the transistors charge carriers increasingly accumulate at the interface formed by the gate dielectric layer and the channel region and thus build up a conductive channel between the source region and the drain region. Hence, the current flow is established by one type of charge carriers only, contrary to the current flow in a bipolar transistor, where both, minority and majority charge carriers, contribute to current flow. Due to this unipolar current flow in field effect transistors, switching speed is significantly faster as compared to bipolar transistors, thereby making the FET, specifically MOS transistor a viable candidate for high-performance applications.
Recently FETs, specifically MOS transistors are increasingly used in power applications. Such applications require the handling of currents up to several tens Ampere or higher and voltages of up to 100 Volt and significantly higher, since in many cases fast switching transistors are also required in switched power supplies, motor controllers, and the like. The high voltages in power applications, however, necessitate specific adaptations in the dopant profiles of the MOS transistors so as to provide for the desired breakdown voltage characteristics. For instance, a so-called drift region is connected to the drain region and thus connects the drain region to the channel region provided. The drift region is basically a semiconductor region having the same basic doping as the drain region, however, at a reduced dopant concentration. This results in a substantially ohmic behaviour of the drift region, thereby generating a corresponding voltage drop across the drift region upon forming a conductive channel. Consequently, the dopant profile in the drain and source regions and their connection to the channel region with an intermediate drift region substantially determine the transistor characteristics in “power applications”.
Field effect transistors may generally be divided into enhancement type transistors and depletion type transistors. While in an enhancement type transistor the channel region does not provide a conductive path when applying zero voltage at the gate electrode structure, depletion type transistors provide a conductive channel at zero gate voltage. Hence, the depletion type transistors are conductive without applying a gate voltage and these depletion transistors can be switched off by applying a gate voltage. For an n-channel transistor this voltage is negative. To this end the depletion type transistor receives an additional doping concentration in the channel region which results in a conductive path between the drain and source regions, which may increasingly be “depleted” of charge carriers upon applying a negative gate-to-source-voltage, thereby finally switching the transistor off when the channel region is fully depleted.
With reference to FIG. 1 a typical transistor configuration of a vertical DMOS transistor 10 and conventional techniques for forming an additional channel region for a depletion mode transistor will be explained in more detail.
Schematically illustrated is a cross-sectional view of said DMOS transistor 10 that is shown in the form of an enhancement type transistor. The transistor 10 comprises a highly doped substrate material 1, which also acts as the drain region or drain terminal of the transistor 10. For an n type transistor example, the drain region 1 is highly n doped. A semiconductor layer 2 is provided as drift region of the transistor 10 and formed above the drain region 1. The drift region has the same conductivity type as the drain region 1, however with a reduced dopant concentration. A well region 5 is formed in the drift region 2 and has inverse conductivity type compared to the drift region 2. A highly doped source region 6 is provided in the well region 5 and thus forms a pn-junction with the well region 5. A region 9 at a surface of the drift region 2 and positioned within the well region 5, laterally adjacent to the source region 6 is referred to as “channel region”, since here a conductive path is forming when an appropriate control voltage is applied to a gate electrode structure 4a, which comprises a gate electrode 4, for instance a doped polysilicon material, and a gate dielectric layer 3, such as a silicon dioxide material, that separates the gate electrode 4 from the channel region 9 and the drift region 2. Furthermore, the transistor 10 comprises an interlayer or intermetal dielectric material 7, which includes openings (not shown) for contacting the gate electrode 4 and for connecting the source region 6 and the well region 5, as indicated by reference sign 8.
The transistor as illustrated in FIG. 1 is typically formed by providing the substrate 1 having the desired dopant concentration, while the drift region 2 receives the reduced dopant concentration, for instance by epitaxially forming a semiconductor material and concurrently incorporating the dopant species therein. The gate structure 4a is provided on the basis of well established deposition and/or oxidation techniques. Thereafter, the well region 5 is formed by an implantation and anneal process. That is, the dopant species of the well region 5 is implanted in the presence of the gate electrode structure 4a, which acts as an implantation mask, thereby achieving a self-aligned position of the well region 5 relative to the gate electrode 4. During the subsequent anneal process a diffusion of the dopants is initiated, wherein the process parameters (temperature and process time) are selected such that the desired lateral “overlap” of the well region 5 with the gate electrode 4 is achieved. It should be appreciated that a vertical diffusion also takes place. Similarly, the dopant species of the source region 6 is implanted in self-aligned manner by using the gate electrode structure 4a and any resist mask as an implantation mask. In a further anneal process the final shape of the source region 6, and possibly of the well region 5, is/are adjusted by initiating a desired degree of diffusion. Finally, the interlayer dielectric material 7 is deposited and the openings are formed therein so as to connect to the contact area 8.
During operation of the transistor 10—for an assumed n-channel transistor—a zero or negative gate-source or gate-well voltage results in a substantially non-conductive state of the channel region 9, except for low leakage currents. Upon applying a positive gate-source voltage increasingly electrons collect at the interface formed by the well region 5 and the gate dielectric layer 3. The electrons recombine with the majority charge carriers (the holes) until the gate-source voltage exceeds a threshold voltage, which represents the voltage level at which excess electrons remain, thereby “inverting” the channel region 9 and forming a conductive channel between the source region 6 and the drift region 2 through the well region 5. It should be appreciated that the transistor's characteristics, such as on-resistance, threshold voltage, and the like are strongly related to the configuration of the dopant profiles of the regions 2, 5, 6.
In order to obtain a depletion mode operation based on the configuration of the transistor 10 as described above, U.S. Pat. No. 4,003,071 (Sadaaki Takagi, Fujitsu) proposes to apply an additional implantation so as to incorporate dopants near the surface of the channel region 9 in order to increase the doping therein such that a conductive path is obtained. Hence, a conductive connection between the source region 6 and the drift region 2 is obtained via the additionally introduced dopants. In the above described example of an n-channel transistor, an n-type dopant species is incorporated into the channel region 9, such as phosphorous, arsenic or antimony at a moderately low implantation dose. In this manner the highly doped drain 1 and source regions 6 are electrically connected in the absence of a gate voltage. On the other hand the conductive channel can be depleted by applying a negative gate voltage, thereby switching off the transistor 10.
U.S. Pat. No. 6,700,160 (Steven Merchant, Texas Instruments) discloses a DMOS transistor having an additional doped region below the gate oxide within the lightly doped drift region 2 and within a portion of the well region 5. However, the operating mode (enhancement type or depletion type) is not changed by this change in configuration.
Generally, providing an additional doped region in the channel region of an enhancement type transistor so as to achieve a depletion mode is a promising approach. However, implanting the additional dopants through the gate electrode or even through the gate dielectric material may result in significant damage of the gate dielectric material, thereby deteriorating the overall transistor performance. On the other hand, incorporating the additional dopants prior to forming the gate dielectric material will cause a pronounced dopant diffusion during the anneal process for aligning the well profile. In particular, a pronounced vertical diffusion into the well region 5 will occur, thereby negatively affecting the overall transistor behaviour. By using appropriate dopant species having a high diffusion coefficient, such as boron, for the well region and having a low diffusion coefficient for the additional channel doping, such as arsenic or antimony, the vertical diffusion into the depth of the well region may be reduced, but cannot be avoided.
When switching off the transistor, however, an early breakdown may occur, since the effective well doping is reduced due to the additional channel doping even if strongly negatively biased. Hence, the space charge region in the well region may extend or punch through to the highly doped source region 6.
FIG. 2 schematically illustrates the results of a simulation in a conventional depletion mode transistor that comprises an additionally doped channel region, wherein the additional dopant species is schematically denoted by reference sign 21. The channel region comprising the additional doping 21 has the inverse doping of the well region 5, as explained above. Here, the status of a negative gate voltage (the off-mode) is illustrated. As indicated by the potential lines even a moderately low voltage between the drain and source may lead to a punch through of the drain potential to the source region 6. A non-desired reduction of the punch through voltage caused by the doping situation for forming the additionally-doped channel region may be compensated by increasing the channel length (for FIG. 1 the horizontal extension of the channel region 9). As evaluated above, the overall dopant profile and thus the channel length is typically adjusted by means of the temperature and the duration of the anneal processes. For example, an increased channel length is obtained by increasing the diffusion activity during the well diffusion, thereby, however, not only increasing the lateral diffusion and thus the channel length, but also increasing the vertical extension of the well region, which may result in a non-desired change of the transistor's characteristics.